1. Field of the Invention
The present invention relates to a bridge-type inverter circuit obtained by forming a switching unit in the shape of an H bridge.
2 Description of the Related Art
When a load of an AC motor, etc. is driven, it may be driven while adjusting a supplied voltage. In this case, a bridge-type inverter circuit obtained by connecting a switching element of a transistor, etc. to an H-shaped bridge is widely used. FIGS. 1 and 2 show an example of a bridge-type inverter circuit. FIG. 1 shows an example driven by 3 power sources while FIG. 2 shows an example driven by a single power source.
First, the bridge-type inverter circuit shown in FIG. 1 includes field-effect transistors (FET) 1 through 4, which are the first through fourth switching units, driven by corresponding drive circuits 1a through 4a. That is, independent drive signals 1b through 4b are respectively provided for the drive circuits 1a through 4a, and the corresponding drive circuits 1a through 4a are driven to alternately drive the FETs 1 and 4 and the FETs 2 and 3. Therefore, three power sources, that is, a direct current power source 5 for driving the drive circuit 1a, a direct current power source 6 for driving the drive circuit 3a, and a direct current power source 7 for driving the drive circuits 2a and 4a are used in this circuit.
On the other hand, the bridge-type inverter circuit shown in FIG. 2 drives the FETs 1 through 4 using a single drive power source, and drives a drive signal 8 (8a, 8b) at a high level (H level) and a low level (L level). For example, the circuit turns on the FET 2 through a resistor R1 when the drive signal 8a indicates the H level, turns on the FET 1 when the drive signal 8a indicates the L level. By repeating this process, the FETs 1 and 2 can be alternately turned on and off. The FETs 3 and 4 not shown in FIG. 2 can also be alternately driven according to the drive signal 8b. The drive signals 8a and 8b have an inverse relationship in output timing of the H level and the L level. That is, the FET 3 is turned on when the FET 2 is ON, and the FET 4 is turned on when the FET 1 is ON, thereby providing the electric power for an alternating current load not shown in FIG. 2.
In FIG. 2, when the drive signal 8a indicates the H level, a transistor 10 is turned on after being provided with a high-level signal through a resistor R4, and sets the FET 1 in an OFF state through the resistor R5. An electrolysis capacitor 11 accumulates an electric charge through a resistor 2 and a diode 9 when the drive signal 8a indicates the H level, and drives the FET 1 as described above when the drive signal 8a turns to the low level.
However, the following problems occur in the above described conventional circuit. First, the circuit shown in FIG. 1 requires three drive power sources 5 through 7, causing a costly device. The drive signals 1b through 4b are independent, and therefore it is difficult to control the signals to prevent the FETs 1 and 2, or 3 and 4 from being simultaneously turned on (to prevent a short circuit).
Similarly, it is important for the circuit shown in FIG. 2 to prevent a short circuit. Therefore, the switching speed of the FET cannot be set high. As a result, the above described circuit can control only up to several tens KHz. For example, a high frequency over a few hundred KHz cannot be controlled.